Capacitors are used in semiconductor devices, such as integrated circuits (ICs) for storing electrical charge. In ICs, such as dynamic random access memory (DRAM), capacitors are used for storage in the memory cells. Typically, capacitors formed in ICs include a lower electrode made of, e.g., polycrystalline silicon (polysilicon), a dielectric layer made of, e.g., tantalum pentoxide and/or barium strontium titantate, and an upper electrode made of, e.g., titanium nitride, titanium, tungsten, platinum or polysilicon.
In recent years, the development of the semiconductor memory device has required higher packing density, the area occupied by a capacitor of a DRAM storage cell shrinks, thus decreasing the capacitance of the capacitor because of its smaller electrode surface area. However, a relatively large capacitance is required to achieve a high signal-to-noise ratio in reading the memory cell. Therefore, it is desirable to reduce the cell dimension and yet obtain a high capacitance. This can be accomplished with a metal electrode capacitor, for example. Also, highly integrated memory devices, such as DRAMs, require a very thin dielectric film for the data storage capacitor. To meet this requirement, the capacitor dielectric film thickness will be below 2.5 nm of SiO.sub.2 equivalent thickness. Use of a thin layer of a material having a higher relative permittivity, e.g. Ta.sub.2 O.sub.5, in place of the conventional SiO.sub.2 or Si.sub.3 N.sub.4 layers is useful in achieving desired performance.
A chemical vapor deposited (CVD) Ta.sub.2 O.sub.5 film can be used as a dielectric layer for this purpose, because the dielectric constant (k) of Ta.sub.2 O.sub.5 is approximately three times that of a conventional Si.sub.3 N.sub.4 capacitor dielectric layer. However, one drawback associated with the Ta.sub.2 O.sub.5 dielectric layer is undesired leakage current characteristics. Accordingly, although Ta.sub.2 O.sub.5 material has inherently higher dielectric properties, Ta.sub.2 O.sub.5 typically may produce poor results due to leakage current. For example, U.S. Pat. No. 5,780,115 to Park et al., discloses the use of Ta.sub.2 O.sub.5 as the dielectric for an integrated circuit capacitor with the electrode layer being formed of titanium nitride (TiN). However, at temperatures greater than 600.degree. C., this type of layered structure has a stability problem because the titanium in the TiN layer tends to reduce the Ta.sub.2 O.sub.5 of the dielectric layer into elemental tantalum.
Traditionally, interconnection between two conductors in a semiconductor device has been provided by a plug structure such as a tungsten plug, for example, for an electrical connection between first and second metal lines. Such structures require three separate processing steps including one for the formation of each of the two conductors and one for the formation of the tungsten plug structure. Additionally, greater interest has been shown by manufacturers of semiconductor devices in the use of copper and copper alloys for metallization patterns, such as in conductive vias and interconnects. Copper, compared to aluminum, has both good electromigration resistance and a relatively low electrical resistivity of about 1.7 .mu.ohm.multidot.cm. Unfortunately, copper is difficult to etch. Consequently, dual damascene processes have been developed to simplify the process steps and eliminate a metal etch step to form copper interconnects. Dual damascene processes are also used with aluminum interconnects.
A dual damascene structure has a bottom portion or via that contacts an underlying conductor and replaces the function of a plug structure in a traditional interconnect structure. The dual damascene structure also has a top portion or inlaid trench that is used for the formation of a second conductor. Because the bottom and top portions of a dual damascene structure are in contact with each other, they can be filled simultaneously with the same conductive material, e.g. copper. This eliminates the need to form a plug structure and an overlying conductive layer in separate processing steps.
Conventionally, in the dual damascene process, capacitors are usually formed in a separate level by depositing a first conductive layer, forming the dielectric therebetween, forming a second conductive layer, and then patterning and etching the layered structure. The conductive layers are typically formed of polysilicon or titanium nitride, for example. Next an oxide is formed over the capacitors and results in surface topographies above the capacitors. This requires chemical mechanical polishing (CMP) to planarize the oxide layer before subsequent layers are formed.
Thus, the conventional process of making capacitors requires additional time due to the etching of the conductive layers as well as the CMP step. Also, if forming a capacitor with metal electrodes, i.e. a metal-insulator-metal (MIM) capacitor, the metal etch step required is not fully compatible with the dual damascene process. In other words, as discussed above, the dual damascene process is used specifically to avoid metal etching; therefore, using a metal etch step within a dual damascene process is undesirable.
As can be seen from the above discussion, there is a need for integration of a high-density metal electrode capacitor which is compatible with the dual damascene process. Furthermore, there is a need for a capacitor dielectric, for such a metal electrode capacitor, that is a high-k, high quality and low leakage dielectric, and which prevents the reduction of the dielectric by the metal of the electrode.